A popular circuit topology for realizing high-speed, high resolution Analog-to-Digital converters is based on the multi-step architecture. U.S. Pat. No. 5,210,537 describes a multistage A/D converter having two cascaded A/D stages of parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second A/D stage information about the quantization error of the first A/D stage as well as the quantization step size to be used to define full-scale at the second A/D stage. The second A/D stage includes a parallel converter for developing a set of less-significant bits representing the ratio of the normal residue signal to the sum of the two residue signals. The most-significant and less-significant sets of bits are combined to provide the final digital output. Errors due to inaccuracies in interstage gain are reduced due to the use of two residue signals for generating the less significant bits.
The major problem in these converters is the transition from one sub-range into another. To be monotonic by design the dual-residue principle can be used. However while this type of converter is monotonic by design the offset on the residue amplifiers still determine the integral non-linearity (INL) of the converter. For example in communication system there are high demands on the linearity (=INL) of AD-converters.
The article xe2x80x9cBackground digital calibration techniques for pipelined ADC""sxe2x80x9d, by Un-Ku Moon and Bang-Sup Song, IEEE Transactions on Circuits and Systemsxe2x80x94II: Analog and digital signal Processing, vol. 44, no. 2, Feb. 1997, pp. 102-109, describes a skip and fill algorithm to digitally self-calibrate pipelined analog to digital converters (ADC""s) in real time. The technique is based on the concept of skipping conversion cycles randomly but filling in data later by non-linear interpolation. At each skipped conversion cycle, a calibration test signal is injected in place of the input signal. However, this skipping plus interpolation leads to less than optimal analog to digital conversion results.
It is, inter alia, an object of the invention to provide an improved analog to digital conversion. To this end, the invention provides an analog to digital converter as defined in the independent claim. An advantageous embodiments are defined in the dependent claim.
A primary aspect of the invention provides an analog to digital converter that comprises a first stage for developing a set of most significant bits from an analog input signal and for producing analog residue signals corresponding to respective differences between the analog input signal and threshold values directly above and below, respectively, the analog input signal, and a second stage for developing a set of lesser significant bits from the analog residue signals. According to the invention, the analog residue signals are reversed. An offset detection unit coupled to the second stage retrieves offset data representative of offset errors, and an offset correction unit corrects the offset errors on the basis of the offset data.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.